<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\dual_ov5640\src\fifo_ping\temp\FIFO\fifo_define.v<br>
C:\Users\hankg\OneDrive\Works\Gowin\dual_ov5640\src\fifo_ping\temp\FIFO\fifo_parameter.v<br>
D:\Gowin\Gowin_V1.9.8\IDE\ipcore\FIFO\data\edc.v<br>
D:\Gowin\Gowin_V1.9.8\IDE\ipcore\FIFO\data\fifo.v<br>
D:\Gowin\Gowin_V1.9.8\IDE\ipcore\FIFO\data\fifo_top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">GowinSynthesis Version</td>
<td>GowinSynthesis V1.9.8</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Oct 21 19:00:20 2021
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>fifo_ping</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 32.367MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 32.367MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 32.367MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 32.367MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 32.367MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.238s, Peak memory usage = 41.027MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 41.027MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 41.027MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 41.027MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>40</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>40</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>21</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>19</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>74</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>66</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNP</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>61</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>25</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>17</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>19</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>42</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>42</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>122(62 LUTs, 42 ALUs, 3 SSRAMs) / 54720</td>
<td>1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>74 / 41997</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 41997</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>74 / 41997</td>
<td>1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>1 / 140</td>
<td>1%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>RdClk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>RdClk_ibuf/I </td>
</tr>
<tr>
<td>WrClk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>WrClk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>RdClk</td>
<td>100.0(MHz)</td>
<td>195.3(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>WrClk</td>
<td>100.0(MHz)</td>
<td>154.9(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.545</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.282</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Equal.wq2_rptr_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Almost_Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>WrClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>WrClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>48</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wq2_rptr_4_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>fifo_inst/Equal.wq2_rptr_4_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_3_s1/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>fifo_inst/Equal.rcount_w_3_s1/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_3_s0/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.rcount_w_3_s0/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_0_s0/I3</td>
</tr>
<tr>
<td>3.287</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_0_s0/F</td>
</tr>
<tr>
<td>3.524</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_0_s/I1</td>
</tr>
<tr>
<td>4.094</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_0_s/COUT</td>
</tr>
<tr>
<td>4.094</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_1_s/CIN</td>
</tr>
<tr>
<td>4.129</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_1_s/COUT</td>
</tr>
<tr>
<td>4.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_2_s/CIN</td>
</tr>
<tr>
<td>4.164</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>4.164</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>4.199</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>4.199</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>4.669</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_4_s/SUM</td>
</tr>
<tr>
<td>4.906</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/awfull_val_s3/I1</td>
</tr>
<tr>
<td>5.461</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/awfull_val_s3/F</td>
</tr>
<tr>
<td>5.698</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/awfull_val_s1/I1</td>
</tr>
<tr>
<td>6.253</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/awfull_val_s1/F</td>
</tr>
<tr>
<td>6.490</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/awfull_val_s4/I1</td>
</tr>
<tr>
<td>7.045</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/awfull_val_s4/F</td>
</tr>
<tr>
<td>7.282</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Almost_Full_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>48</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Almost_Full_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Almost_Full_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.292, 66.851%; route: 1.896, 29.535%; tC2Q: 0.232, 3.614%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.199</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.628</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Full_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>WrClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>WrClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>48</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>fifo_inst/Full_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/n29_s1/I0</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/n29_s1/F</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_0_s/I1</td>
</tr>
<tr>
<td>2.655</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_0_s/COUT</td>
</tr>
<tr>
<td>2.655</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_1_s/CIN</td>
</tr>
<tr>
<td>2.691</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_1_s/COUT</td>
</tr>
<tr>
<td>2.691</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_2_s/CIN</td>
</tr>
<tr>
<td>2.726</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_2_s/COUT</td>
</tr>
<tr>
<td>2.726</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_3_s/CIN</td>
</tr>
<tr>
<td>2.761</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_3_s/COUT</td>
</tr>
<tr>
<td>2.761</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_4_s/CIN</td>
</tr>
<tr>
<td>2.796</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_4_s/COUT</td>
</tr>
<tr>
<td>2.796</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_5_s/CIN</td>
</tr>
<tr>
<td>2.832</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_5_s/COUT</td>
</tr>
<tr>
<td>2.832</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_6_s/CIN</td>
</tr>
<tr>
<td>2.867</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_6_s/COUT</td>
</tr>
<tr>
<td>2.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_7_s/CIN</td>
</tr>
<tr>
<td>2.902</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_7_s/COUT</td>
</tr>
<tr>
<td>2.902</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_8_s/CIN</td>
</tr>
<tr>
<td>2.937</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_8_s/COUT</td>
</tr>
<tr>
<td>2.937</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_9_s/CIN</td>
</tr>
<tr>
<td>3.407</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>fifo_inst/Equal.wbinnext_9_s/SUM</td>
</tr>
<tr>
<td>3.644</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wgraynext_8_s0/I1</td>
</tr>
<tr>
<td>4.199</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>fifo_inst/Equal.wgraynext_8_s0/F</td>
</tr>
<tr>
<td>4.436</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wfull_val_s6/I1</td>
</tr>
<tr>
<td>4.991</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wfull_val_s6/F</td>
</tr>
<tr>
<td>5.228</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wfull_val_s11/I3</td>
</tr>
<tr>
<td>5.599</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wfull_val_s11/F</td>
</tr>
<tr>
<td>5.836</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wfull_val_s0/I1</td>
</tr>
<tr>
<td>6.391</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>6.628</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Full_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>48</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Full_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.875, 67.202%; route: 1.659, 28.774%; tC2Q: 0.232, 4.024%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.880</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.947</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>RdClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>RdClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>31</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>fifo_inst/Empty_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/n33_s0/I0</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/n33_s0/F</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_0_s/I1</td>
</tr>
<tr>
<td>2.655</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_0_s/COUT</td>
</tr>
<tr>
<td>2.655</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_1_s/CIN</td>
</tr>
<tr>
<td>2.691</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_1_s/COUT</td>
</tr>
<tr>
<td>2.691</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_2_s/CIN</td>
</tr>
<tr>
<td>2.726</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_2_s/COUT</td>
</tr>
<tr>
<td>2.726</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_3_s/CIN</td>
</tr>
<tr>
<td>2.761</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_3_s/COUT</td>
</tr>
<tr>
<td>2.761</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_4_s/CIN</td>
</tr>
<tr>
<td>2.796</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_4_s/COUT</td>
</tr>
<tr>
<td>2.796</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_5_s/CIN</td>
</tr>
<tr>
<td>2.832</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_5_s/COUT</td>
</tr>
<tr>
<td>2.832</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_6_s/CIN</td>
</tr>
<tr>
<td>2.867</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_6_s/COUT</td>
</tr>
<tr>
<td>2.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_7_s/CIN</td>
</tr>
<tr>
<td>2.902</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_7_s/COUT</td>
</tr>
<tr>
<td>2.902</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_8_s/CIN</td>
</tr>
<tr>
<td>2.937</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_8_s/COUT</td>
</tr>
<tr>
<td>2.937</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_9_s/CIN</td>
</tr>
<tr>
<td>3.407</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>fifo_inst/rbin_num_next_9_s/SUM</td>
</tr>
<tr>
<td>3.644</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rgraynext_8_s0/I1</td>
</tr>
<tr>
<td>4.199</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.rgraynext_8_s0/F</td>
</tr>
<tr>
<td>4.436</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/n141_s0/I0</td>
</tr>
<tr>
<td>4.985</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/n141_s0/COUT</td>
</tr>
<tr>
<td>4.985</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/n142_s0/CIN</td>
</tr>
<tr>
<td>5.020</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/n142_s0/COUT</td>
</tr>
<tr>
<td>5.257</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rempty_val_s1/I2</td>
</tr>
<tr>
<td>5.710</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rempty_val_s1/F</td>
</tr>
<tr>
<td>5.947</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Empty_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>31</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Empty_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.431, 67.471%; route: 1.422, 27.966%; tC2Q: 0.232, 4.563%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.356</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.471</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Full_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Equal.wptr_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>WrClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>WrClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>48</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>fifo_inst/Full_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/n29_s1/I0</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/n29_s1/F</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_0_s/I1</td>
</tr>
<tr>
<td>2.655</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_0_s/COUT</td>
</tr>
<tr>
<td>2.655</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_1_s/CIN</td>
</tr>
<tr>
<td>2.691</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_1_s/COUT</td>
</tr>
<tr>
<td>2.691</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_2_s/CIN</td>
</tr>
<tr>
<td>2.726</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_2_s/COUT</td>
</tr>
<tr>
<td>2.726</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_3_s/CIN</td>
</tr>
<tr>
<td>2.761</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_3_s/COUT</td>
</tr>
<tr>
<td>2.761</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_4_s/CIN</td>
</tr>
<tr>
<td>2.796</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_4_s/COUT</td>
</tr>
<tr>
<td>2.796</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_5_s/CIN</td>
</tr>
<tr>
<td>2.832</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_5_s/COUT</td>
</tr>
<tr>
<td>2.832</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_6_s/CIN</td>
</tr>
<tr>
<td>2.867</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_6_s/COUT</td>
</tr>
<tr>
<td>2.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_7_s/CIN</td>
</tr>
<tr>
<td>2.902</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_7_s/COUT</td>
</tr>
<tr>
<td>2.902</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_8_s/CIN</td>
</tr>
<tr>
<td>2.937</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_8_s/COUT</td>
</tr>
<tr>
<td>2.937</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_9_s/CIN</td>
</tr>
<tr>
<td>2.972</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wbinnext_9_s/COUT</td>
</tr>
<tr>
<td>2.972</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.wbinnext_10_s/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>fifo_inst/Equal.wbinnext_10_s/SUM</td>
</tr>
<tr>
<td>3.679</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wgraynext_9_s0/I1</td>
</tr>
<tr>
<td>4.234</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wgraynext_9_s0/F</td>
</tr>
<tr>
<td>4.471</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.wptr_9_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>48</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wptr_9_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Equal.wptr_9_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.429, 67.302%; route: 0.948, 26.269%; tC2Q: 0.232, 6.429%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.356</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.471</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Equal.rptr_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>RdClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>RdClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>31</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>fifo_inst/Empty_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/n33_s0/I0</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/n33_s0/F</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_0_s/I1</td>
</tr>
<tr>
<td>2.655</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_0_s/COUT</td>
</tr>
<tr>
<td>2.655</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_1_s/CIN</td>
</tr>
<tr>
<td>2.691</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_1_s/COUT</td>
</tr>
<tr>
<td>2.691</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_2_s/CIN</td>
</tr>
<tr>
<td>2.726</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_2_s/COUT</td>
</tr>
<tr>
<td>2.726</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_3_s/CIN</td>
</tr>
<tr>
<td>2.761</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_3_s/COUT</td>
</tr>
<tr>
<td>2.761</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_4_s/CIN</td>
</tr>
<tr>
<td>2.796</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_4_s/COUT</td>
</tr>
<tr>
<td>2.796</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_5_s/CIN</td>
</tr>
<tr>
<td>2.832</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_5_s/COUT</td>
</tr>
<tr>
<td>2.832</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_6_s/CIN</td>
</tr>
<tr>
<td>2.867</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_6_s/COUT</td>
</tr>
<tr>
<td>2.867</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_7_s/CIN</td>
</tr>
<tr>
<td>2.902</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_7_s/COUT</td>
</tr>
<tr>
<td>2.902</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_8_s/CIN</td>
</tr>
<tr>
<td>2.937</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_8_s/COUT</td>
</tr>
<tr>
<td>2.937</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_9_s/CIN</td>
</tr>
<tr>
<td>2.972</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_9_s/COUT</td>
</tr>
<tr>
<td>2.972</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_10_s/CIN</td>
</tr>
<tr>
<td>3.442</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>fifo_inst/rbin_num_next_10_s/SUM</td>
</tr>
<tr>
<td>3.679</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rgraynext_9_s0/I1</td>
</tr>
<tr>
<td>4.234</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/Equal.rgraynext_9_s0/F</td>
</tr>
<tr>
<td>4.471</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>fifo_inst/Equal.rptr_9_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>31</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rptr_9_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Equal.rptr_9_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.429, 67.302%; route: 0.948, 26.269%; tC2Q: 0.232, 6.429%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>
